CERES RISC-V Core

Bu bölüm, CERES RISC-V işlemci çekirdeğinin tüm modüllerini kapsar.

Hiyerarşi

rtl/core/
├── cpu.sv                    # Top-level CPU
├── hazard_unit.sv            # Pipeline hazard handling
├── stage01_fetch/            # Instruction Fetch
├── stage02_decode/           # Instruction Decode
├── stage03_execute/          # Execute (ALU, MUL/DIV)
├── stage04_memory/           # Memory Access
├── stage05_writeback/        # Write-back
├── mmu/                      # Memory Management
└── pmp_pma/                  # Physical Memory Protection

Modüller

Top-Level

Modül	Açıklama
CPU	Top-level CPU modülü
Hazard Unit	Pipeline hazard detection ve forwarding

Pipeline Stages

Stage	Modüller
Fetch	Instruction fetch, branch prediction, RAS
Decode	Instruction decode, register file
Execute	ALU, multiplier, divider, CSR
Memory	Load/store operations
Writeback	Register write-back

Memory System

Modül	Açıklama
Cache	I-Cache ve D-Cache
Memory Arbiter	Instruction/Data arbiter
WB Interconnect	Wishbone interconnect
PMA	Physical Memory Attributes

Pipeline Diagram

┌─────────┐   ┌─────────┐   ┌─────────┐   ┌─────────┐   ┌─────────┐
│  FETCH  │──▶│ DECODE  │──▶│ EXECUTE │──▶│ MEMORY  │──▶│WRITEBACK│
└─────────┘   └─────────┘   └─────────┘   └─────────┘   └─────────┘
     │             │             │             │             │
     ▼             ▼             ▼             ▼             ▼
  Branch       Register       ALU/MUL       Load/       Register
  Predict      File Read      DIV/CSR       Store       Write