Level RISC-V Core¶

This section covers all modules of the Level RISC-V processor core.

Hierarchy¶

rtl/core/
├── cpu.sv                    # Top-level CPU
├── hazard_unit.sv            # Pipeline hazard handling
├── stage01_fetch/            # Instruction Fetch
├── stage02_decode/           # Instruction Decode
├── stage03_execute/          # Execute (ALU, MUL/DIV)
├── stage04_memory/           # Memory Access
├── stage05_writeback/        # Write-back
├── mmu/                      # Memory Management
└── pmp_pma/                  # Physical Memory Protection

Modules¶

Top-Level¶

Module	Description
CPU	Top-level CPU module
Hazard Unit	Pipeline hazard detection and forwarding

Pipeline Stages¶

Stage	Modules
Fetch	Instruction fetch, branch prediction, RAS
Fetch (prefetch) + microarch notes	Next-line prefetcher, Prefetcher wrapper, Microarch ideas — fetch & memory
Decode	Instruction decode, register file
Execute	ALU, multiplier, divider, CSR
Execute (MUL/DIV variants)	mul_int, mul_pipelined, Wallace tree, divu_int, divu_pipelined
Memory	Load/store operations
Memory (helpers)	Store buffer, Cache logger
Writeback	Register write-back

Memory System¶

Module	Description
Cache (unified)	Top-level unified cache documentation
I-cache	Standalone instruction cache
D-cache	Standalone data cache
FENCE.I helper	`dcache_fencei` write-back FSM
L2 cache	Non-blocking multi-bank L2 (`nbmbmp_l2_cache`)
Memory Arbiter	Instruction/Data arbiter
WB Interconnect	Wishbone interconnect
PMA	Physical Memory Attributes

Pipeline Diagram¶

┌─────────┐   ┌─────────┐   ┌─────────┐   ┌─────────┐   ┌─────────┐
│  FETCH  │──▶│ DECODE  │──▶│ EXECUTE │──▶│ MEMORY  │──▶│WRITEBACK│
└─────────┘   └─────────┘   └─────────┘   └─────────┘   └─────────┘
     │             │             │             │             │
     ▼             ▼             ▼             ▼             ▼
  Branch       Register       ALU/MUL       Load/       Register
  Predict      File Read      DIV/CSR       Store       Write